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| ADVANCE INFORMATION - CONFIDENTIAL The Leader in CMOS Image Sensors ICM320T Preliminary Data Sheet V1.0 3.2 Megapixel QXGA Digital Color CMOS Image Sensor General Description The ICM320T is a high resolution, low power, small form factor device 3.2Megapixel digital color CMOS image sensor. The ICM320T is based on IC Media's high performance, wide acceptance angle 2.575m TopazPixelTM technology. The ICM320T supports a 1/2.7" optical format with short track lengths of less than 7.0mm. High responsivity, low noise and image quality enhancing filters results in excellent image quality even in low light conditions. The 2,048x1536 pixel array operates at up to 16fps at full QXGA resolution, and at progressively higher frame rates at 1/4 sub-sampled (1024x768) and 1/16 sub-sampled (512x384) resolutions. Low power consumption and few required external discrete devices makes the ICM320T ideal for small form factor, battery-operated mobile consumer devices. It consumes only 70mW at 15fps at QXGA and standby current is 8A. The ICM320T image sensor's registers are programmed through an efficient, two-wire serial control interface (SIF) enabling flexible control of the sensor's operating modes. It outputs 10-bit raw Bayer (RGB) pixel samples synchronized to the associated pixel clock (PCLK) as well as vertical and horizontal synchronization signals (VSYNC/HSYNC). Applications * * * * * * * Cellular phone cameras Personal digital assistants Digital still cameras and camcorders Notebook and desktop PC cameras Video telephony and conferencing equipment Security systems Industrial and environmental systems Key Performance Parameters Parameter Optical format Active pixels Physical pixels Pixel size Sensor area Responsivity Dynamic range Signal-to-noise ratio (SNR) Dark signal Programmable Gain Typical Value 1/2.7 inches 2,048 x 1,536 2,122 x 1,556 2.575 m x 2.575 m 5.27mm x 3.96mm 1.4 V/Lux-sec 58 dB 43 dB 5mV/sec Analog: Up to 4x Digital: 1/256 to 64x for individual Bayer pattern pixels Minimum: 34 s Maximum: ~ 126 s Up to 16 fps QXGA 1/4-rate: 1,024x768 1/16-rate: 512x384 6 to 64 MHz 2.8 V (analog) 1.8 V (digital core) 1.8-3.3 V (digital I/O) 70 mW (16fps@64 MHz) 8 A -20oC to +70oC Bare die in wafer form 48-pin CLCC14.22 Exposure time Frame rate Subsampling Input clock frequency Power supply Feature Overview * * * * * * * * * * * Wide acceptance angle pixel architecture enabling compact camera module form factors Very low active and stand-by power consumption Very good low light sensitivity Automatic dark level offset compensation Image enhancing noise cancellation filters Fast global reset mechanical shutter support High frame rate at full image resolution Excellent color reproduction for vibrant pictures Low complexity, two-wire serial control interface On-chip 11-bit column analog-to-digital converters with correlated double sampling Programmable exposure time, frame rate, subsampling, window size, analog and digital gain, horizontal and vertical image inversion, and dead pixel removal Power consumption Power down mode power Operating temperature Packaging Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 1 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T Table of Contents General Description........................................................................................................................................... 1 Feature Overview .............................................................................................................................................. 1 Applications....................................................................................................................................................... 1 Key Performance Parameters ............................................................................................................................ 1 Functional Description ...................................................................................................................................... 9 Image Sensor Array ........................................................................................................................................... 9 Exposure Time................................................................................................................................................. 10 Digital Gain Control ........................................................................................................................................ 10 Analog Gain Control ....................................................................................................................................... 10 Analog Gain Calibration.................................................................................................................................. 10 Pixel Timing and Function Control ................................................................................................................. 10 Subsampling Schemes ..................................................................................................................................... 10 Dark Level Compensation ............................................................................................................................... 10 Dead Pixel Filtering......................................................................................................................................... 10 Pixel Noise Filtering........................................................................................................................................ 10 Power Supply Noise Filtering.......................................................................................................................... 11 Fast Global Reset............................................................................................................................................. 11 Output Data Format ......................................................................................................................................... 11 Pixel Clock ...................................................................................................................................................... 11 Power Down Mode.......................................................................................................................................... 11 Output Pin State Control.................................................................................................................................. 11 Serial Control Interface (SIF) .......................................................................................................................... 11 SIF Registers ................................................................................................................................................... 13 Absolute Maximum Ratings ............................................................................................................................ 20 Electrical Characteristics ................................................................................................................................. 21 DC Characteristics....................................................................................................................................... 21 AC Characteristics....................................................................................................................................... 23 Sensor Timing ................................................................................................................................................. 24 Reset Timing ............................................................................................................................................... 24 Pixel Output Timing .................................................................................................................................... 24 QXGA Full Resolution Mode Line Timing................................................................................................. 25 QXGA Full Resolution Mode Frame Timing.............................................................................................. 25 1/4-Rate Subsampling Mode Line Timing .................................................................................................. 26 1/4-Rate Subsampling Mode Frame Timing................................................................................................ 26 1/16-Rate Subsampling Mode LineTiming ................................................................................................. 27 1/16-Rate Subsampling Mode Frame Timing.............................................................................................. 27 Mechanical Information .................................................................................................................................. 28 Ordering Information....................................................................................................................................... 29 Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 2 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T List of Figures Figure 1. System Block Diagram .............................................................................................................................. 5 Figure 2. Cell Phone Camera Module COB Application Circuit .............................................................................. 5 Figure 3. ICM320T Bare Die Pad Diagram............................................................................................................... 6 Figure 4. ICM320T 48-Pin CLCC14.22 Package...................................................................................................... 8 Figure 5. Image Sensor Array.................................................................................................................................... 9 Figure 6. Fast Global Reset ..................................................................................................................................... 11 Figure 7. Reset Timing ............................................................................................................................................ 24 Figure 8. Pixel Output Timing................................................................................................................................. 24 Figure 9. Default QXGA Line Timing for 2200 PCLKs ......................................................................................... 25 Figure 10. Default QXGA Frame Timing - Change Registers 0x4/0x15 to 0x0010 (H) ........................................ 25 Figure 11. Default 1/4-Rate Line Timing for 1100 PCLKs..................................................................................... 26 Figure 12. Default 1/4-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H).................................... 26 Figure 13. Default 1/16-Rate Line Timing for 570 PCLKs..................................................................................... 27 Figure 14. Default 1/16-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H)................................... 27 Figure 15. 48-pin CLCC14.22 Mechanical Drawing............................................................................................... 28 List of Tables Table 1. ICM320T Bare Die Pad Assignments ......................................................................................................... 6 Table 2. SIF Registers Descriptions ........................................................................................................................ 13 Table 3. Absolute Maximum Ratings...................................................................................................................... 20 Table 4. DC Characteristics..................................................................................................................................... 21 Table 5. AC Characteristics..................................................................................................................................... 23 Table 7. Ordering Information................................................................................................................................. 29 Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 3 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 This page is intentionally left blank ICM320T Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 4 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T Figure 1. System Block Diagram Figure 2. Cell Phone Camera Module COB Application Circuit Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 5 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T Figure 3. ICM320T Bare Die Pad Diagram Table 1. ICM320T Bare Die Pad Assignments (continued) Pad 1 2 3 4, 14, 24 5, 13, 25 6 7 8, 33 9, 30, 31, 41 10 11, 32 12 15 16 17 18 19 20 21 22 Name RAMP RSTN PWR_DOWN VDDA GNDA SIF_SDA SIF_SCL VDDCORE GND CLKIN VDDIO PCLK DOUT [0] DOUT [1] DOUT [2] DOUT [3] DOUT [4] DOUT [5] DOUT [6] DOUT [7] Class* A, O D, I D, I, N P P D, I/O D, I/O P P D, I P D, O D, O D, O D, O D, O D, O D, O D, O D, O Function Analog ramp output Chip reset, active low Power down control, 0: power down, 1: active Sensor analog power (2.8V) Sensor analog ground SIF data SIF clock Sensor digital core power (1.8V) Sensor digital ground Clock input Sensor I/O power (1.8-3.3V) Pixel clock output Data output bit 0 Data output bit 1 Data output bit 2 Data output bit 3 Data output bit 4 Data output bit 5 Data output bit 6 Data output bit 7 3/14/2005 Copyright 2005, IC Media Corporation http://www.ic-media.com/ Page 6 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 1. ICM320T Bare Die Pad Assignments (continued) Function Data output bit 8 Data output bit 9 Vertical sync signal Reserved. Do not connect. Horizontal sync signal Output enable. 0: enable, 1: disable Reserved. Do not connect. LSB of SIF slave address SIF master/slave selection. 0: slave, 1: master (auto load from EEPROM after reset) 38 N/C3 N/A Reserved. Do not connect. 39 N/C4 N/A Reserved. Do not connect. 40 N/C5 N/A Reserved. Do not connect. 42 RES_REF A, I Resistor to ground: 12 k @ for up to 16fps QXGA (64MHz PCLK) 16 k @ for up to 12fps QXGA (48MHz PCLK) 33 k @ for up to 6fps QXGA (24MHz PCLK) * Class Codes: A - analog signal, D - digital signal, I - input, O - output, P - power or ground, U - internal pull-up, N - internal pull-down, N/C - no connection. Pad 23 26 27 28 29 34 35 36 37 Name DOUT [8] DOUT [9] VSYNC N/C1 HSYNC OEN N/C2 SIF_ID SIF_MS Class* D, O D, O D, O N/A D, O D, I N/A D, I, N D, I, N ICM320T Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 7 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T Figure 4. ICM320T 48-Pin CLCC14.22 Package Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 8 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Functional Description The ICM320T is a single-chip digital colorimaging device. It includes a 2048x1536 pixel sensor array, 2122 column-level ADCs, and correlated double sampling (CDS) circuitry. Writing into the SIF interface, which can address the register file consisting of 8-bit registers, sets all the programmable parameters. The output format is 10-bit raw Bayer RGB data, together with horizontal and vertical synchronization signals. after sampling the current signal) from the signal value. The sensor output is approximately proportional to the amount of received light, ranging from 0 to 1024. There are several dummy rows and columns surrounding the array; 64 on the left side and 10 on the top, right and bottom sides. The outer 60 of the 64 dummy pixels on the left side and outer 6 of the 10 dummy pixels on the top, right and bottom sides are covered with dark filters. The remaining dummy pixels are active pixels covered by Red, Green, and Blue color filters in a Bayer pattern. These pixels can be used for color interpolation. The 2048x1536 (QXGA) size active signal pixel array, pixel (64, 10) through pixel (2111, 1545), is also covered by an array of Red, Green, and Blue color filters in a Bayer pattern. See Figure 5 for a detailed layout of the sensor array. ICM320T Image Sensor Array The image array consists of 2122x1556 pixels. Each pixel has a light-sensitive photo diode and a set of control and transfer transistors. At the beginning of the pixel exposure cycle, a row of pixels is pre-charged to its maximum value. Then the row is exposed to light for several lines worth of time and sampled by the ADC. A CDS process subtracts the reset value (sampled right Figure 5. Image Sensor Array Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 9 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Exposure Time To accommodate different illumination requirements, you can change the exposure time on the ICM320T by adjusting registers 0x1C and 0x1D. The exposure time is measured in terms of the time to read out one line of data. The time for processing one line is equal to the pixel clock period times the frame width. The frame width is stored in registers 0x0C and 0x0D. The exposure time for one full resolution default line width of 2200 pixel clocks is 34 s when the pixel clock is 64 MHz. applications. The pixel analog data path timing is controlled by the default settings or by downloading a pixel configuration table. Register 0x02[4] makes the selection. Pixel configuration tables are sequentially downloaded into registers 0x04, 0x05, and 0x06 while incrementing the 0x03 address pointer. ICM320T Subsampling Schemes The ICM320T supports subsampling for viewfinder and other reduced data rate output modes. It supports sub-sampled resolutions in the 1/4-rate 1024x768 and 1/16-rate 512x384 formats. The 1/4-rate mode maximum frame rate is twice the maximum full resolution frame rate. The peak 1/16-rate frame rate is four times the maximum full resolution frame rate. Subsampling modes are selected through register 0x52[7:4]. Digital Gain Control The ICM320T digital gain control feature is one of the methods you can use to control image quality. Adjusting the digital gain is generally used for minor changes, either to balance color or to adjust the overall image luminance. The gain range is from 1/256 to 8 of the four Bayer pattern pixels. Gain changes require changes to two types of registers; the per Bayer color channel gain value registers 0x20-0x28, and the magnitude of change register 0x52[3:0]. Dark Level Compensation The ICM320T supports automatic dark level compensation with programmable offset. The automatic dark level compensation algorithm supports user programmable hysteresis to prevent oscillation of automatic exposure algorithms in companion devices. The hysteresis parameters are set using register 0x3B[2:0]. The algorithm in enabled by register 0x3B[7]. Analog Gain Control The ICM320T supports up to 4x analog gain control for low light operation. Four analog gain settings are programmable using register 0x28. The default value 0x00, corresponds to 1x gain, which is used for normal light. Other settings are 0x81: 2x gain, 0x92: 3x gain and 0xA3: 4x gain. Modified analog gain settings are activated by writing 0x1 into register 0x00[7]. Dead Pixel Filtering The ICM320T supports dead pixel filtering for both full QXGA resolution and sub-sampled 1/4rate and 1/16-rate resolutions. The filter is only applied to pixels outside the high and low dead pixel filter thresholds defined in registers 0x42 through 0x45. The filter is enabled and disabled using register 0x51[3]. Analog Gain Calibration The analog gain can be calibrated by adjusting the maximum analog input and the maximum ADC output so that they have the same dynamic range. To enable automatic gain calibration, write 0x1 into register 0x00[1]. Pixel Noise Filtering The ICM320T implements pixel noise suppression filtering for improved image quality under low light conditions for both full QXGA resolution and sub-sampled 1/4-rate and 1/16rate resolutions. The pixel noise suppression filter implements a two or four pixel averaging across adjacent pixels of the same color space in sub sampled resolutions. Register 0x51[2:0] is used to enable and disable two pixel or four pixel averaging respectively. 3/14/2005 Pixel Timing and Function Control The ICM320T has a software-controlled pixel analog data path. This feature allows fine-tuning of the sensor's performance and makes the sensor highly adaptable to a wide range of Copyright 2005, IC Media Corporation http://www.ic-media.com/ Page 10 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Power Supply Noise Filtering The ICM320T implements a power supply noise filter for removal of power supply induced row noise for improved low light image quality. The row noise filter can be automatically enabled when analog gain is applied, or manually controlled. Register 0x3B[5] is used to select manual or automatic mode. Manual control of the filter is done through register 0x3B[6]. The row noise filter can be programmed to a residual image offset value. This value is set through register 0x3C. When the clock frequency changes, the RSET resistor on the RES_REF pin as well as the initialization file may also need to be changed. The value of the RSET resistor is inversely proportional to the ADC clock frequency. At 128 MHz ADC clock, the RSET is 12 k; at 96 MHz ADC clock, it is 16 ; at 48 MHz ADC clock, it is 33 k. ICM320T Power Down Mode When the PWR_DOWN pin is de-asserted, the chip goes into power down mode. In this state, the internal clock is stopped. The PWR_DOWN pin is not synchronized with the device clock. The power down takes effect immediately. On the assertion of the PWR_DOWN pin, the sensor must wait at least 10 s to leave the power down mode to prevent the sensor from operating in an unstable state. Fast Global Reset The ICM320T implements a fast global reset feature in support of low cost mechanical shutters. With fast global reset, the ICM320T image sensor array can be reset in 1.5ms @ 5fps (PCLK=24 MHz). An example fast global reset image capture sequence is described in Figure 6. Output Pin State Control The state of the video output pins PCLK, VSYNC, HSYNC, DOUT[9:0] is controlled by the OEN pin or SIF register 0x4A[5:0]. Upon power on reset or hard reset, the video pin output state is determined by the configuration or the OEN pin. If the OEN pin is asserted (active low), the video outputs are enabled. If the OEN pin is de-asserted, the video output pins are tri-stated. SIF register 0x4A[5:0] can be used to override the video pin output states independent of the OEN pin configuration. The video output pins are divided into three categories; CLK (PCLK), SYNC (VSYNC, HSYNC) and DATA (DOUT[9:0]). The output state for each output pin category can be independently controlled. Figure 6. Fast Global Reset Output Data Format During normal operation, the output format is 10-bit raw data on the DOUT[9:0] data pins. In addition to the data pins, the chip also outputs VSYNC, HSYNC, and PCLK. The length and polarity of the VSYNC and HSYNC signals can be adjusted through registers 0x01[2:1] for polarity; 0x18 and 0x19 for HSYNC length; 0x1A and 0x1B for VSYNC length . The line and frame timing can be adjusted through registers 0x0C-0x0F. Serial Control Interface (SIF) The ICM320T sensor is fully compatible with the I2C interface. Register programming is through the SIF interface (SIF_SCL and SIF_SDA pins). The default address for the 7-bit SIF device is 0x20. The SIF_ID pin can configure the last bit of the device address. The ICM320T can operate in either SIF master mode or in slave mode right after power up, depending on the pull-up or pull-down of the SIF_MS pin. When the SIF_MS pin is pulled down during power up, the ICM320T's SIF interface is 3/14/2005 Pixel Clock The pixel clock, PCLK, is a multiple of the external clock. Although the output data is 10 bits, the internal ADC is 11 bits to minimize quantization noise. Therefore, the ADC clock is running at twice the frequency of the PCLK. Copyright 2005, IC Media Corporation http://www.ic-media.com/ Page 11 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 operated as a SIF slave device, waiting to be controlled by an external SIF master such as a microprocessor. When SIF_MS is pulled-up during power up, the SIF interface is first acting as a SIF master device trying to read from an external SIF EEPROM. After that, the SIF interface returns to slave mode. ICM320T Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 12 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 SIF Registers Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Y Frame Boundary Update Y ICM320T 0x00 PART CONTROL Processing control [0] 0: Normal mode. 1: Single frame mode. [1] Slope adjustment enable [2] Exposure time control. Writing a `1' will activate the new value set in 0x1C and 0x1D, when read back from it. A `0' means that the exposure time change is finished. A `1' means that the exposure time change is still in progress. [6:3] Frame rate for different ADC clock frequencies. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 ADC clock frequency 48 MHz 96 MHz 128 MHz 6 fps 12 fps 16 fps 3 fps 6 fps 8 fps 2 fps 4 fps 5 fps 1 fps 2 fps 2.3 fps 0.85 fps 1.7 fps 1.9 fps 0.6 fps 1.2 fps 1.0 fps 0.4 fps 0.8 fps 0.5 fps 0.2 fps 0.4 fps 0x00 [7] Latent change. Writing a `1' means that the changed latent registers now start taking effect. When the entire operation is done, the read back value of this bit will change from `1' to `0'. Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 13 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Frame Boundary Update ICM320T 0x01 TIMING CONTROL (LSB) 0x02 TIMING CONTROL (MSB) Timing control [0] Column count enable, set to 0 when filling register file, set to 1 when normal operation [1] HSYNC polarity 0: active low, 1: active high The DOUT[5] pin determines the initial value [2] VSYNC polarity 0: active low, 1: active high The DOUT[6] pin determines the initial value [3] Auto dark correction enable When this bit is set, register 0x3B will decode which autodark correction scheme will be used [4] Timing select, 0: register file timing, 1: default timing [6] Flash polarity, 0: active low, 1: active high [7] Blank polarity, 0: active low, 1: active high [8] IRST select, 0: from register file, 1: from IRST_NUMBER register [10] Capture: when in single frame mode, writing a 1 here will start a frame capture [11] Dead column removal mode, 0: color, 1: black-and-white [12] Out-of-array exposure pointer control, 0: point to row 487, 1: point to row 490 (a non-existent row) [13] Column stop, 0: sensor column counter stop at 649 when exceeding real array, 1: sensor column counter keeps counting. 0x03 PIXEL CONFIGURATION TABLE INDEX [4:0] Index to the pixel configuration table register file. 0x04 PIXEL CONFIGURATION TABLE DATA (L) 0x05 PIXEL CONFIGURATION TABLE DATA (M) 0x06 PIXEL CONFIGURATION TABLE DATA (H) Reserved. 0x07 PIXEL CONFIGURATION TABLE LENGTH [4:0] Pixel configuration table register file length 0x08 LOAD PIXEL CONFIGURATION TABLE DATA Writing into this register causes the pixel configuration table data in registers 0x04-0x06 to be written into the pixel configuration table entry that is indexed by register 0x03. 0x09 through 0x0B Reserved 0x0C FRAME WIDTH (LSB) 0x0D FRAME WIDTH (MSB) [10:0] Defines the frame width. The frame width must be more than AD_COL_BEGIN+ 2068. Copyright 2005, IC Media Corporation http://www.ic-media.com/ 0x0011 N N 0x00 N N 0x000000 0x00 0x01 N N N N N N 0x0000 0x0898 (2200) N Y N Y 3/14/2005 Page 14 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Frame Boundary Update ICM320T 0x0E FRAME HEIGHT (LSB) 0x0F FRAME HEIGHT (MSB) [15:0] Defines the frame height. The frame height must be more than AD_ROW_BEGIN + 1556. 0x10 IMAGE READOUT CONTROL (LSB) 0x11 IMAGE READOUT CONTROL (MSB) [9:0] Beginning of the active line in terms of column position. [10] Left-right mirror image enable. [11] Image flip up-down image. 0x14 ROW START ADDRESS (LSB) 0x15 ROW START ADDRESS (MSB) [15:0] The beginning of the active frame in terms of row position. 0x18 HSYNC PULSE WIDTH (LSB) 0x19 HSYNC PULSE WIDTH (MSB) [10:0] Defines the HSYNC pulse width, which is the end of the horizontal sync in terms of column position. 0x1A VSYNC PULSE WIDTH (LSB) 0x1B VSYNC PULSE WIDTH (MSB) [15:0] Defines the VSYNC pulse width, which is the end of the vertical sync in terms of row position. 0x1C EXPOSURE TIME CONTROL (LSB) 0x1D EXPOSURE TIME CONTROL (MSB) [15:0] Exposure time in terms of number of rows. 0x20 GAIN BAYER CHANNEL 1 (LSB) 0x21 GAIN BAYER CHANNEL 1 (MSB) [10:0] Bayer channel 1 gain coefficient. (Gr) in unsigned 3.8 (default) format. 0x22 GAIN BAYER CHANNEL 2 (LSB) 0x23 GAIN BAYER CHANNEL 2 (MSB) [10:0] Bayer channel 2 gain coefficient. (R) in unsigned 3.8 (default) format. 0x24 GAIN BAYER CHANNEL 3 (LSB) 0x25 GAIN BAYER CHANNEL 3 (MSB) 10:0] Bayer channel 3 gain coefficient. (B) in unsigned 3.8 (default) format. 0x26 GAIN BAYER CHANNEL 4 (LSB) 0x27 GAIN BAYER CHANNEL 4 (MSB) [10:0] Bayer channel 4 gain coefficient. (Gb) in unsigned 3.8 (default) format. 0x071C (1820) 0x0064 (100) Y Y Y Y 0x000A (10) 0x0040 (64) 0x0003 (3) 0x071B (1819) 0x0100 (256) 0x0100 (256) 0x0100 (256) 0x0100 (256) Y Y Y Y Y Y N Y Y Y Y Y Y Y Y Y Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 15 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Y Frame Boundary Update Y ICM320T 0x28 ANALOG GAIN CONTROL [7:4] Analog gain settings for low light operation 0x00 0x00: 1x gain (default) 0x81: 2x gain 0x92: 3x gain 0xA3: 4x gain Others: Reserved 0x29 through 0x3A Reserved. 0x3B ROW NOISE FILTER AND DARK LEVEL COMPENSATION 0x00 [7]: Enable frame based auto dark correction 1: enable 0: disable [6]: Enable row noise filter 1: enable 0: disable Note: bit[7] should be set to `0' if row noise filter is enabled. [5]: Auto enable row noise filter 1: Automatic activation mode 0: Manual activation mode Setting this bit will turn on row noise filter automatically when analog sensor gain is applied [2:0]: Frame based auto dark correction hysteresis control 0: 4 frames 1: 8 frames 2: 16 frames 0x3C ROW NOISE FILTER IMAGE OFFSET Image offset value when row noise filter is enabled. 0x0a 0x3D FRAME BASED DARK COMPENSATION IMAGE OFFSET Image offset value for frame based dark level compensation. 0x00 0x3E through 0x3F Reserved. 0x40 DARK OFFSET SUBTRAHEND (LSB) 0x41 DARK OFFSET SUBTRAHEND (MSB) [9:0] When auto dark correction is disabled, serve as the 0x0000 subtrahend for dark correction 0x42 HIGH DEAD PIXEL THRESHOLD (LSB) 0x43 HIGH DEAD PIXEL THRESHOLD (MSB) [9:0] Apply dead pixel removal algorithm only to pixels 0x003FF above HighLimit (1023) N Y N N Y Y N Y N N Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 16 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Frame Boundary Update ICM320T 0x44 LOW DEAD PIXEL THRESHOLD (LSB) 0x45 LOW DEAD PIXEL THRESHOLD (MSB) [9:0] Apply dead pixel removal algorithm only to pixels below LowLimit. 0x46 through 0x49 Reserved. 0x4A VIDEO OUTPUT CONTROL [7] : Soft reset (auto clear) [6] : Reserved. [5]: Set PCLK pin output state during standby mode 1: PCLK set to Low (`0') during stand-by mode 0: PCLK tri-stated (Z') during stand-by mode [4]: Set SYNC pin output states during standby mode 1: HSYNC/VSYNC set to Low (`0') during stand-by mode 0: HSYNC/VSYNC tri-stated (Z') during stand-by mode [3]: Set DATA pin output states during standby mode 1: DOUT[9:0] set to Low (`0') during stand-by mode 0: DOUT[9:0] tri-stated (Z') during stand-by mode [2]: PCLK pin output state during video mode 1: PCLK output tri-stated 0: PCLK output active [1]: SYNC pin output state during video mode 1: HSYNC/VSYNC outputs tri-stated 0: HSYNC/VSYNC outputs active [0]: DATA pin output state during video mode 1: DATA[9:0] outputs tri-stated 0: DATA[9:0] outputs active 0x4B to 0x50 Reserved. 0x0000 N N 0x00 N N Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 17 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register N Frame Boundary Update Y ICM320T 0x51 DEAD PIXEL AND AVERAGING FILTER CONTROL 0x00 [0]: Column average for 1/4-rate subsampling (2-point average) 1: Enable 0: Disable [1]: Column average for 1/16-rate subsampling (4-point average) 1: Enable 0: Disable [2]: Row average for both sub-sampling modes 1: Enable 0: Disable [3]: Dead pixel filter for sub-sampling mode 1: Enable 0: Disable 0x52 OUTPUT FORMAT CONTROL 0x00 [3:0] Global digital gain 0x0: 1x gain (default) 0x1: 2x gain 0x2: 4x gain 0x3: 8x gain Others: 1x gain [7:4] Output format 0x0: Normal mode (default) 0x1: Reserved. 0x2: 1/16-rate subsampling mode (1024x768 format) 0x3: 1/4-rate subsampling mode (512x384 format) 0x4: Control signal 0x5: Sensor row 0x6: Sensor column Others: Normal mode 0x53 to 0x81 Reserved. 0x82 DEVICE ID 0x83 DEVICE ID [3:0] Sub ID. Can be configured using SIF 0xB100 [15:4] Device ID, default 0xB10. Can be configured using (45312) SIF. 0x84 FLASH START POSITION (LSB) 0x85 FLASH START POSITION (MSB) [15:0] Flash begin position in terms of rows. 0x0614 (1556) N Y N N N Y Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 18 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 2. SIF Registers Descriptions Bit Description (continued) Default Affected by Latent Register Frame Boundary Update ICM320T 0x86 FLASH END POSITION (LSB) 0x87 FLASH END POSITION (MSB) [15:0] Flash end position in terms of rows 0x071C (1820) N Y 0x88 through 0x9C Reserved. 0x9D MAXIMUM EXPOSURE TIME INCREASE (LSB) 0x9E MAXIMUM EXPOSURE TIME INCREASE (MSB) [15:0] Maximum step size for exposure time increase. 0x0618 (1560) 0x9F through 0xB3 Reserved 0xB4 PLL CONFIGURATION (LSB) 0xB5 PLL CONFIGURATION (MSB) PLL pre-divider (M), multiplier (N) and post-divider (R) 0x0001 settings for generation of the on-chip ADC clock (ADCLK) (1) based on the input clock (CLKIN) frequency. The M, N and R settings must be such that the ADC clock is 2x the frequency of the desired output PCLK. The following equation is used to derive the ADCLK based on a given CLKIN and M, N and R settings: ADCLK = N x CLKIN / (M x R) [11:10]: PLL post divider (R) [9:8] : PLL pre-divider (M) [5:0] PLL multiplier (N) PLL N, R and M Settings [5:0] [11:10] N=1 0x0 R = 1 (D) 0x0 N = 2 (D) 0x1 R = 2 0x1 N=3 0x2 R = 3 0x2 N=4 0x3 R = 4 0x3 N=8 N = 16 Y Y N Y 0x0 0x1 0x2 0x3 0x4 0x5 [9:8] M = 1 (D) M=2 M=3 M=4 0xB6 through 0xFF Reserved * Reserved bits must not be changed Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 19 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Absolute Maximum Ratings Table 3. Absolute Maximum Ratings Specification Supply voltage VDDA VDD VDDIO Rating 3.6 V 2.1 V 3.6V -0.3 V to VDDIO +0.3V -0.3 V to VDDIO +0.3V 0 to 65C 2,000 V 200 V 125 mA 240C for 20 seconds ICM320T Input voltage Output voltage Storage temperature ESD rating Human body model 1 Machine model 2 3 Latch-up protection Convection or IR reflow temperature 4 Notes: 1 EIA/JESD22-A114 2 EIA/JESD22-A115 3 EIA/JESD78 4 IPC/JEDEC-J-STD-020C Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 20 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Electrical Characteristics DC Characteristics (VDDC=1.8V, VDDIO=2.5V, VDDA=2.8V, TA=25C) Table 4. DC Characteristics (continued) Symbol VDDA VINA VOUTA TSTG VDDA VDDC VDDIO VIN IDDA IDDC Parameter Absolute Power Supply Absolute Input Voltage Absolute Output Voltage Storage Temperature Analog Operating Power Supply Digital Core Operating Power Supply Digital I/O Operating Power Supply Operating Input Voltage Analog Supply Current (15 fps @ 64 MHz) Digital Core Supply Current (15 fps @ 64 MHz) Digital I/O Supply Current (15 fps @ 64 MHz) Input Low Current Input High Current Tri-state Leakage Current Input Capacitance Output Minimum -0.3 -0.3 -0.3 0 2.7 1.7 1.8 0 14 12 25 2.8 1.8 2.5 Rating Typical Unit Maximum 3.6 VDDIO + 0.3 VDDIO + 0.3 65 2.9 2.1 3.3 VDDIO V V V C V V V V mA mA ICM320T IDDIO 4 mA IIL IIH IOZ CIN COUT -1 -1 -10 3 3 1 1 10 A A A pF pF 3/14/2005 Copyright 2005, IC Media Corporation http://www.ic-media.com/ Page 21 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Table 4. DC Characteristics (continued) Symbol Parameter Minimum CBID VIL VILS VIH VIHS VOL VOH RL Capacitance Bi-directional Buffer Capacitance Input Low Voltage Schmitt Input Low Voltage Input High Voltage Schmitt Input High Voltage Output Low Voltage Output High Voltage Input Pullup/down Resistance Rating Typical 3 0.3 * VDDIO 1.1 0.7 * VDDIO 1.8 0.4 0.7 * VDDIO 12 Unit Maximum pF V V V V V V K ICM320T Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 22 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T AC Characteristics Table 5. AC Characteristics Parameter Setup time Hold time Rise time Minimum Typical Maximum Condition No input pin needed for Setup and Hold time requirements. SDA/SCL are subject to I2C protocol. TBD 25pf load Pin Fall time TBD 25pf load Clock duty DCG range 40 50 16 60 PCLK, HSYNC, VSYNC, DOUT[10:0] PCLK, HSYNC, VSYNC, DOUT[10:0] % Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 23 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Sensor Timing The following sections discuss the timing requirements and formats for the ICM320T image sensor. Note that the timing requirements are related to the pixel clock and the format depends on the subsampling mode. ICM320T Reset Timing The reset timing reset signal RSTN must be asserted for more than two stable clock cycles. In addition, the VDD voltage ramp must be above 90% of its specified value for more than two stable clock cycles as shown in Figure 7. Figure 7. Reset Timing Pixel Output Timing The pixel data and timing output signals are DOUT [9:0], PCLK, VSYNC, and HSYNC. Data should be latched at the rising edge of the PCLK. The VSYNC and HSYNC signals are asserted and de-asserted at the falling edge of the PCLK. See Figure 8. Figure 8. Pixel Output Timing Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 24 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T QXGA Full Resolution Mode Line Timing For the default QXGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal will be low for 64 PCLK clock cycles. After 100 PCLK clock cycles, DOUT [9:0] will output ten cycles of dummy pixel data followed by 2048 cycles of image data and ten cycles of dummy pixel data. Another 32 cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 9. Figure 9. Default QXGA Line Timing for 2200 PCLKs QXGA Full Resolution Mode Frame Timing For the default QXGA frame timing, the timing unit for the frame is derived from one line-time unit, which is 2200 PCLKs. Frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be low for three line-time units. Sixteen line-time units from the start of the frame, DOUT [9:0] will output ten lines of dummy pixel data, followed by 1536 lines of image data and another ten lines of dummy pixel data. 248 lines after the image pixel data, the VSYNC signal will be de-asserted again to start a new frame. See Figure 10. Figure 10. Default QXGA Frame Timing - Change Registers 0x4/0x15 to 0x0010 (H) Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 25 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T 1/4-Rate Subsampling Mode Line Timing For the default 1/4-rate (1024x768) line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal will be low for 32 PCLK clock cycles. After 50 PCLK clock cycles, DOUT [9:0] will output five cycles of dummy pixel data, followed by 1024 cycles of image data and another five cycles of dummy pixel data. Sixteen cycles after the last dummy pixel data, the VSYNC signal will be de-asserted again to start a new line. See Figure 11. Figure 11. Default 1/4-Rate Line Timing for 1100 PCLKs 1/4-Rate Subsampling Mode Frame Timing For the default 1/4-rate (1024x768)frame timing, the timing unit for the frame is derived from one line-time unit, which is 1100 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be low for three line-time units. Eight line-time units from the start of the frame, DOUT [9:0] will output five lines of dummy pixel data, followed by 240 lines of image data and another five lines of dummy pixel data. Two lines after the last dummy pixel data, the VSYNC signal will be de-asserted again to start a new frame. See Figure 12. Figure 12. Default 1/4-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H) Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 26 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 ICM320T 1/16-Rate Subsampling Mode LineTiming For the default 1/16-rate (512x384) line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal will be low for 16 PCLK clock cycles. After 25 PCLK clock cycles, DOUT [9:0] will output three cycles of dummy pixel data, followed by 512 cycles of image data and another three dummy pixel data. Seven clock cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 13. Figure 13. Default 1/16-Rate Line Timing for 570 PCLKs 1/16-Rate Subsampling Mode Frame Timing For the default 1/16-rate (512x384) frame timing, the timing unit for the frame is derived from one linetime unit, which is 550 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be low for three line-time units. Four line-time units from the start of the frame, DOUT [9:0] will output three lines of dummy pixel data followed by 384 lines of image data and another three lines of dummy pixel data. Eleven (11) clock cycles later, the VSYNC signal will be de-asserted again to start a new frame. See Figure 14. Figure 14. Default 1/16-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H) Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 27 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Mechanical Information ICM320T Figure 15. 48-pin CLCC14.22 Mechanical Drawing Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 28 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Ordering Information Table 6. Ordering Information Description Bare die in wafer form - no grinding, wafer thickness of 74025m Bare die in wafer form - back grinding, wafer thickness of 30012.5m 48-Pin CLCC14.22 package, (for evaluation only) Part Number ICM320TNADA ICM320TGAda ICM320Tca ICM320T Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 29 3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor Preliminary Data Sheet V1.0 Important notice: This document contains information about a new product. IC Media Corp. reserves the right to make any changes without further notice to any product herein to improve the design, function or quality and reliability. No responsibility is assumed by IC Media Corp. for its use or for any infringements of patents of third parties that may result from its use. ICM320T IC Media Corporation 5201 Great America Pkwy., Suite 422, Santa Clara, CA 95054, U.S.A. Phone: +1-408-213-2000 Fax: +1-408-213-2450 Email: sales@ic-media.com Web Site: www.ic-media.com IC Media International Corporation 2F, No. 61, ChowTze Street., NeiHu District Taipei, Taiwan, R.O.C. Phone: +886-2-2657-7898 Fax: +886-2-2657-8751 Email: ap.sales@ic-media.com.tw Web Site: www.ic-media.com.tw Copyright 2005, IC Media Corporation http://www.ic-media.com/ 3/14/2005 Page 30 |
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